Search results
1 – 1 of 1
Article
Publication date: 1 January 1982
Kunihiko Edamatsu, Tetsuo Kiuchi, Yoshiaki Isono, Shiro Naruse and Akira Momose
An automated power transistor chip sorting apparatus and position recognition algorithm have been developed at Fuji Electric. The apparatus inspects each chip on a wafer cassette…
17
Abstract
An automated power transistor chip sorting apparatus and position recognition algorithm have been developed at Fuji Electric. The apparatus inspects each chip on a wafer cassette, and picks out the good chips and arranges them on a chip tray cassette, at a recognition rate of 0.3 seconds per chip.
1 – 1 of 1